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keep exp/coll
859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 | }
static gint column2index(GtkTreeViewColumn * column)
{
gint i;
for (i = 0; i < COL_NUMBER; i++) {
GtkTreeViewColumn *col;
col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), i);
if (col == column)
return i;
}
return -1;
}
|
keep exp/coll
836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 | break;
case S_INT:
case S_HEX:
case S_STRING:
default:
break;
}
}
static void toggle_sym_value(struct menu *menu)
{
if (!menu->sym)
return;
sym_toggle_tristate_value(menu->sym);
if (view_mode == FULL_VIEW)
|
Per test, 4BYTE Indicator bit doesn't set after EN4B, which
doesn't match spec(MX25L25635E), so skip the check below.
874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 | if (idBuf[0] != MFGID_MXIC)
{
if (isEn)
{
while (! SPIM_Is4ByteModeEnable(u32NBit)) { }
}
else
{
while (SPIM_Is4ByteModeEnable(u32NBit)) { }
}
}
ret = 0;
}
return ret;
}
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should be timer type
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 | device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_hs_timer_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_hs_timer_control;
device->user_data = timer;
/* register a character device */
return rt_device_register(device, name, flag);
}
/***************************************************************************//**
* @brief
|
should be adc type
706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 | device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_adc_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_adc_control;
device->user_data = adc;
/* register a character device */
return rt_device_register(device, name, flag);
}
/***************************************************************************//**
* @brief
|
should be acmp type
212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 | device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
device->init = rt_acmp_init;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = rt_acmp_control;
device->user_data = acmp;
/* register a character device */
return rt_device_register(device, name, flag);
}
/***************************************************************************//**
* @brief
|
use_internal_dma
312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 | reg = GET_REG(mmc_obj->base + OFFSET_SDC_CTRL);
reg |= MMC_CTRL_INT_ENABLE;
#ifdef MMC_USE_DMA
reg |= MMC_CTRL_USE_DMA;
#endif
SET_REG(mmc_obj->base + OFFSET_SDC_CTRL, reg);
//set timeout param
SET_REG(mmc_obj->base + OFFSET_SDC_TMOUT, 0xffffffff);
//set fifo
reg = GET_REG(mmc_obj->base + OFFSET_SDC_FIFOTH);
reg = (reg >> 16) & 0x7ff;
reg = ((0x2 << 28) | ((reg/2) << 16) | ((reg/2 + 1) << 0));
SET_REG(mmc_obj->base + OFFSET_SDC_FIFOTH, reg);
}
|
power on ? ctrl by gpio ?
308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 | MMC_ClearRawInterrupt(mmc_obj, MMC_INT_STATUS_ALL);
MMC_SetInterruptMask(mmc_obj, 0x0);
//fixme: use_internal_dma
reg = GET_REG(mmc_obj->base + OFFSET_SDC_CTRL);
reg |= MMC_CTRL_INT_ENABLE;
#ifdef MMC_USE_DMA
reg |= MMC_CTRL_USE_DMA;
#endif
SET_REG(mmc_obj->base + OFFSET_SDC_CTRL, reg);
//set timeout param
SET_REG(mmc_obj->base + OFFSET_SDC_TMOUT, 0xffffffff);
//set fifo
reg = GET_REG(mmc_obj->base + OFFSET_SDC_FIFOTH);
|
check HLE_INT_STATUS
224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 | return 0;
}
int MMC_ResetFifo(struct fh_mmc_obj *mmc_obj)
{
rt_uint32_t reg, tick, timeout;
tick = rt_tick_get();
timeout = tick + RT_TICK_PER_SECOND / 10; //100ms
reg = GET_REG(mmc_obj->base + OFFSET_SDC_CTRL);
reg |= 1 << 1;
SET_REG(mmc_obj->base + OFFSET_SDC_CTRL, reg);
//wait until fifo reset finish
while(GET_REG(mmc_obj->base + OFFSET_SDC_CTRL) & MMC_CTRL_FIFO_RESET)
|
lock
spin_lock_irqsave(&chip->lock, flags);
367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 | reg = GET_REG(base + REG_GPIO_SWPORTA_DDR);
reg |= (1 << gpio);
SET_REG(base + REG_GPIO_SWPORTA_DDR, reg);
reg = GET_REG(base + REG_GPIO_SWPORTA_DR);
if(val)
reg |= (1 << gpio);
else
reg &= ~(1 << gpio);
SET_REG(base + REG_GPIO_SWPORTA_DR, reg);
//spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
|